
interface tlm_sys_if(
  input bit clk
///  ip4_int_if.test_dr dr,
///  ip4_int_if.test_mo mo
);
  
///  clocking cb @(posedge clk);
///    default input #1step output #1ns;
///    output dr_ise2spa = dr.ise2spa,
///           dr_spa2ise = dr.spa2ise,
///           dr_spu2spa = dr.spu2spa,
///           dr_spa2spu = dr.spa2spu,
///           dr_rfm2spa = dr.rfm2spa,
///           dr_spa2rfm = dr.spa2rfm,
///           dr_spa2dse = dr.spa2dse,
///           dr_dse2eif = dr.dse2eif,
///           dr_eif2dse = dr.eif2dse,
///           dr_rfm2dse = dr.rfm2dse,
///           dr_dse2rfm = dr.dse2rfm,
///           dr_spu2dse = dr.spu2dse,
///           dr_dse2spu = dr.dse2spu,
///           dr_ise2dse = dr.ise2dse,
///           dr_dse2ise = dr.dse2ise,
///           dr_tlb2dse = dr.tlb2dse,
///           dr_dse2tlb = dr.dse2tlb;
///  endclocking
  
///  default clocking cb @(posedge clk);
///    default input #1step output #1ns;
///    input ise2spa, spa2ise, spu2spa, spa2spu, rfm2spa, spa2rfm,
///          spa2dse, dse2eif, eif2dse, rfm2dse, dse2rfm, spu2dse,
///          dse2spu, ise2dse, dse2ise, tlb2dse, dse2tlb;
///  endclocking

 	modport mods(
   	input clk
   );
endinterface
